Test Engineer

12 Months

San Jose, CA

Description:

JOB DUTIES:

Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design.

Key skills are software (System Verilog, C/C++, object oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.

EXPERIENCE AND EDUCATION:

Bachelors and 0-2 years experience, or Masters and 2+ years experience;

Requires demonstrated technical expertise in functional verification of microprocessor ...