Formal Verification Engineer (RTL to Netlist / Netlist to Netlist)

Experience Range: 3 to 15+ Years

Location: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune

Role Overview

The Formal Verification Engineer is responsible for ensuring functional equivalence and correctness of ASIC and SoC designs across design transformations such as RTL-to-Gate and Gate-to-Gate (ECO, DFT, low-power, CTS) flows. The role heavily uses formal equivalence checking and property-based formal verification to guarantee correctness without exhaustive simulation, working closely with RTL, DFT, STA, Physical Design, and Signoff teams to achieve first-pass silicon success.

Core Responsibilities (All Levels)

• Perform formal equivalence checking (LEC) between RTL and synthesized netlists
• Perform Netlist-to-Netlist equivalence across ECO, DFT...