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STA Signoff Engineer

Mirafra Technologies | Mumbai, India | Posted May 29, 2026

Position Overview

Job Description – STA Engineer (Genus / Low Power)

About the Role

We are looking for skilled and passionate STA Engineers with strong expertise in timing analysis, timing closure, and low-power methodologies to join our VLSI team.

Job Title :- STA Engineer – Genus / Low Power

Experience :- 3+ Years

Location :- Bangalore

Notice Period :- Immediate to 30 Days Preferred

Key Responsibilities

- Perform Static Timing Analysis (STA) and timing closure activities
- Work on low-power timing methodologies and signoff flows
- Handle timing constraints development and validation
- Debug and resolve timing violations across different design stages
- Collaborate with PD, Synthesis, and Design teams for timing convergence
- Support ECO implementation and signoff activities

Required Skills

- Strong knowledge of STA concepts and timing closure
- Hands-on experience with Genus / Primetime tools

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