Job Description

Our client is expanding their Physical Design and timing function and is looking for a Senior STA Engineer, Top Level to support timing constraints and timing closure across complex SoC designs.

In this role, you will create, review and verify block and top level timing constraints. You will work closely with physical implementation, RTL, verification and architecture teams to ensure clean and reliable timing closure for advanced semiconductor programs.

Location : Barcelona, Spain - Hybrid

Responsibilities

• Create and verify block and top level timing constraints
• Support static timing analysis across complex SoC designs
• Work with implementation teams to resolve timing issues
• Define and review SDC constraints
• Support clock strategy, reset strategy and timing exceptions
• Collaborate with RTL, physical implementation and architecture teams
• Analyze timing...