Sr. Staff Digital Verification Engineer

Job Description

- Understand the expected functionality of designs.

- Design and develop verification environment

- Improve verification architecture and flow

- Run RTL and gate-level simulations/daily regression.

- Code/functional coverage development, analysis and closure.

Qualifications

- Bachelor or master degree in CS/ME.

- Minimum of 5 years’ experience.

- Familiar with Systemverilog, UVM verification.

- Have verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).

- Independent and self-managing.

- Familiar with UVM source code or key UVM mechanism

- Familiar with industry standard verification tools and flow.

- Familiar with basic computer architecture

**Additional qualifications**

- Good IC verification skills and basic knowledge of logic and ci...