<b>Job Summary (Sr. Design for Test Engineer)</b><br /> <br /> - Minimum 5 7+ years of DFT (Design for Test) experience, including Scan Insertion, ATPG, MBIST, and JTAG (IEEE 1149.1) Insertion & Verification.<br /> - 2 3 years of recent experience in the semiconductor industry is required.<br /> - Proficient in DFT implementation for advanced nodes (3nm/5nm), targeting Networking chips and IP blocks (including PLL and SerDes).<br /> - Hands-on expertise in Mentor Tessent, Cadence Modus, Synopsys Tetramax, and VCS simulation tools.<br /> - Skilled in low-power DFT methodologies and multi-million gate SoCs for networking, consumer, and IP products.<br /> - Strong scripting abilities in Perl, Shell, and TCL for DFT flow automation and enhancement.<br /> - Responsible for RTL checks, scan insertion, ATPG pattern generation (compressed/uncompressed), pattern simulation (timing/non-timing), and mismatch debug.<br /> - ...