Job Description:

Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and analyzing coverage.
Develop a constrained-random verification environment using UVM.
Work closely with architecture & Design teams.
Initiate and implement flow and environment improvements to scale with growing project complexity.
Work closely with Verification teams to enable smooth execution and high quality.

Additional Positions:

Category:

Job Qualifications:

BSc/ MSc in Electrical Engineering or Computer Science

At least 5 years of experience in verification

Knowledge in design and verification tools and methodologies

Knowledge of UVM System Verilog.

Knowledge in Unix-based environments.

Developed UVM environments from scratch

Excellent communication and problem-solving skills.

Thinks outsi...