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Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog)

Akuaro | barcelona, Spain | Posted June 08, 2026

Position Overview

Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog)

Overview

At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major innovation initiatives, our partner is assembling a world-class engineering team in Barcelona. They are now seeking a Senior Verification Engineer with expertise in SystemVerilog and UVM to ensure their next generation of high-performance silicon meets the highest quality standards.

Contract: Permanent – Internal team of our partner

Why This Role Is Unique

  • Join the forefront of Europe’s semiconductor revolution in CPU design and verification.
  • Verify cutting-edge RISC-V processors destined for high-performance computing applications.
  • Use the lat...

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