I have an exciting opportunity for a Senior Staff Verification Engineer to join a global R&D organisation. In this role, you will be responsible for developing SystemVerilog UVM testbench environments for IP-level verification, as well as designing and implementing new UVM verification components.

You will ensure that verification environments meet all sign-off criteria, including functional coverage, functional safety requirements, and testbench qualification. A key aspect of the role will be representing the verification perspective in design reviews, working closely with design teams, and contributing to the ongoing development of verification strategy and testbench architecture across the business.

Key Requirements

• Minimum of 7 years’ experience in hardware verification, ideally at IP level, using SystemVerilog and UVM
• Advanced expertise in UVM, SystemVerilog, and SystemVerilog Assertions (SVAs)
• Experience developing verification pla...