TetraMem - Accelerate The World in Singapore is looking for a skilled RTL Design Engineer to lead design and verification efforts for ASIC/SoC products. The candidate will be responsible for integrating IP blocks, conducting PPA analysis, and mentoring junior engineers.

Qualifications include an MS or PhD in Electrical Engineering with significant experience in RTL design, Verilog/ SystemVerilog expertise, and prior involvement in startup environments. TetraMem values diversity and is an equal opportunity employer, providing a supportive and inclusive atmosphere.