Become a Senior RTL Designer at AMD, driving innovation in IP design for PCI Express technology. This role emphasizes collaboration and creative problem-solving in a supportive team environment.
As an ASIC Design Engineer, you will be integral to developing high-performance RTL solutions for servers and GPUs. Your expertise in Verilog HDL and multiple clock domains will help shape AMD's cutting-edge computing initiatives. With a focus on quality and system performance, this position allows for both individual and collaborative achievements.
Key Responsibilities:
• Innovate in IP RTL design for PCIe applications
• Work alongside architects on next-gen micro-architectural features
• Implement techniques for low power consumption
• Ensure adherence to timing, LINT, and CDC requirements
• Support ASIC verification and debugging processes
Requirements:
• Strong background in RTL coding using Verilog HDL
• Familiarity with designs involving multiple clock domain...