About The Role We are looking for a Senior Physical Design Engineer to execute physical implementation of high‑speed PCIe IP and sub‑system for an AI chip.
You will own the full physical design flow from netlist to GDSII, working closely with circuit design, DFT, and verification teams to deliver silicon‑proven, high‑performance designs on leading‑edge process nodes.
What You'll Do - Own end‑to‑end physical design flow: floorplanning, placement, CTS, routing, STA, physical verification and signoff for PCIe controller and PHY blocks.
- Perform timing closure for high‑speed PCIe Gen 4/5/6 interfaces across PVT corners.
- Drive power integrity analysis including IR drop and electromigration (EM) across the power delivery network.
- Achieve physical verification closure including DRC, LVS, and ERC signoff using Calibre tool.
- Work with RTL and synthesis teams to provide feedback on logic restructuring for timing and ar...