UST in Penang, Malaysia is seeking a highly skilled Physical Design Engineer to oversee all aspects of physical design including Place & Route and STA analysis for advanced semiconductor technologies. You will work on multimillion gate SoC designs and engage in full-custom analog and mixed-signal layout.

The ideal candidate must have strong expertise in major EDA tools such as Cadence and Synopsys, and a solid background in digital logic design. Self-motivation and adaptability to a dynamic environment are essential.