Mandatory Requirement: 

• 10+ years of industry experience in analog/mixed-signal layout design in advanced process nodes (2nm–16nm, preferably TSMC).
• Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations.
• Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic-to-layout (S2L) flow.
• Experience with FinFET and/or Gate-All-Around (GAA) process technologies.
• Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures.
• Experience leading tape-outs, including design documentation, sign-off checks, and cross-team coordination.
• Good communication skills, both written and oral. The ability to articulate their thought process and...