Responsibilities

• Digital Layout of MS- IPs and Subsystems (RTL2GDS flow)
• Automation, scripting and maintenance of Digital Layout integration
• IR drop and EM Analysis using Apache RedHawk tool suites
• Sign‑off Layout verification and extraction
• Physical synthesis, as well as STA and timing closure

Qualifications

• Bachelor or Master Degree in Electronics Engineering or similar discipline
• 1-5 years of experience in the field of Digital Layout
• Understanding of Synopsys Tool chain (Fusion Compiler, ICC2, DC, Prime time) and/or Cadence Tool chain (Innovus, Tempus)
• Know‑how within Calibre Layout Verification
• RTL2GDS knowledge with main focus on Digital physical implementation and overall Digital Design understanding with TCL, Perl, Python writing and understanding
• A high-quality mindset on own work and you are a team player
• Good English verbal ...