Position Overview
Senior IP Verification Engineer
You will
Take full responsibility for verification of a design, being block or sub-systemDefine and implement UVM based test environmentsBreak-down Requirements and create Verification Specifications, including verification strategy for the design object and associated verification planExecuting Verification Strategy, with creating UVM test benchesDevelop, run and debug test casesWork with Coverage Closure to reach Quality goalsContinuously improve and optimize ways of workingGenerate documentationDevelop competence in technical domain
To be successful in the role you must have A MSc degree in a technical field or the equivalent level of education8+ years’ experience from verification using System Verilog and UVM.Experience in developing verification test plans and directed/randomized test casesGood team cooperation...