Responsibilities: Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout. Create and maintain reusable IPs for AI/in-memory computing. Support Post-Si testing to ensure product functionality and quality. Mentor junior engineers to facilitate their professional growth. Contribute to design reviews for improved product performance and reliability. Stay current on RTL design methodologies for efficiency and quality. Collaborate with cross-functional teams for successful product development. Requirements: Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on
RTL/SoC/digital design
. Proficient in
Verilog and SystemVerilog. Proficient in VCS, Verdi,...