Job Description:

Responsibilities

• Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level.
• Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development.

Required Experience and Skills

• 10+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience
• Deep expertise in Processor Subsystem, ARM cores, SoC verification, Bus Fabric.
• Expertise in developing testbenches using System Verilog and UVM
• Experience using directed and constrained-random test methodologies, coverage closure and gate-level simulations
• Strong object-oriented programming knowledge using SystemVerilog
• Strong problem-solving and debuggin...