In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to:
• Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis；
• Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure；
• Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation,...