Physical Designer Engineer
▌ Responsibilities
Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging
Multiple tasks including but not limited to: back-end physical implementation from gate-level netlist to GDSII, layout design of digital/analog chips, including PR, PV, IR signoff, PPAC optimization, and STA/Spice signoff
▌ Requirements
Understanding of the IC development
Regret to inform that only shortlisted candidates will be notified.
EA Registration Number: R
Business Registration Number: W.