Join Astera Labs in Toronto as a Physical Design Engineering Manager, focusing on complex SoC designs. Lead a talented team while driving ASIC execution and enhancing connectivity solutions.

With over ten years of relevant experience and two years of team leadership, Astera Labs seeks a motivated manager to steer the Signal Connectivity Group. You'll use your hands-on expertise in the physical design flow to guide the implementation of high-speed solutions like PCIe and Ethernet retimers. Your leadership will be pivotal in progressing projects from RTL to GDSII.

Key Responsibilities: • Drive physical design execution from floorplan to tapeout • Lead a team of physical design engineers in Toronto • Ensure design convergence across multiple disciplines and vendors • Establish best practices and quality checks for design flows • Collaborate with global teams to maintain standards

Requirements: • Bachelor's in Electrical Engineering; Master's preferred • 10+ year...