Req ID: JR96245 – New College Graduate – CMOS & Metallization Test Structure Design and Layout
Semiconductor Design Engineer 2
Relocation Level: TBD
Responsibilities - Support process development activities through memory cell‑based test structure solutions by actively engaging with Process Integration, Product and Die Design, Electrical Characterization, Advanced Mask Development and Design Rule teams.
- Interpret electrical DUT (Device under Test) definition and build completed TEGs (Test Element Groups) with high confidence functionality on Silicon.
- Implement novel solutions as the need arises to study the failure mechanisms and to monitor the health of silicon.
- Assist with parametric correlation and debug to ensure design accuracy.
- Verify and validate test structure documentation and related parametric information.
Minimum Qualifications - Master’s degree in electrical, Computer, or Microele...