Job Title:Memory Layout EngineerLocation: Milpitas, CA or Irvine, CA Number of days onsite – (Onsite 5 days/week) MUST-HAVE SKILLS:
- Familiarity with PCIe/PCI Express-based designs
- Strong understanding of Verilog/SystemVerilog and UVM
- Exposure to ASIC development flow
- Experience with SoC design/verification
- Experience in RTL integration, debugging, and functional verification at SoC level
- Collaborate with cross-functional teams to ensure design quality and timely delivery
- gen6 or gen5
8 to 10 years of experience - minimum 8-10 years of PCIe experience.
We are looking for a high-caliber engineer with rich PCIe experience to own the end-to-end system design for our next-generation NVMe S...