Elevate analog design expertise with Celero Communication Inc. as a Lead High-Speed Analog Layout Engineer in Irvine, CA, San Jose, CA, or Ottawa, Canada. Drive the layout design of cutting-edge analog IP blocks while mentoring team members and collaborating across functions.
As a principal engineer in our semiconductor start-up, you will lead the design of complex analog/mixed-signal IP blocks critical for AI and data center systems. Your role entails guiding layout development for high-performance circuits while working closely with circuit designers and CAD teams. Your significant experience in analog layout design will be instrumental in achieving excellence in our state-of-the-art projects.
Key Responsibilities:
• Lead design of complex analog/mixed-signal layout macros
• Optimize layouts through collaboration with schematic designers
• Mentor junior engineers on best practices in layout design
• Perform LVS, DRC, PERC, ERC, and other signoff checks
• Contribu...