Role : FPGA Lead:

Experiecne : 8-15years:

Notice Period : Immediate to 30 Days

Work Mode : 5 Days office

Job Description (JD):

We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of AMD-Xilinx FPGA Architecture. In this role, you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on video connectivity subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the low latency video connectivity systems. You will be also responsible for RTL coding of blocks specified by you or others. Additionally, you will be responsible for various front-end methodology flows that include resource optimization, clock domain crossing, and reset doma...