RTL FPGA Design Engineer

Experience: 2 to 4 Years

Location: Hyderabad, India.

Job Description:

- Minimum of 2 years of RTL design and development experience, preferably in a customer facing role
- Minimum of 2 years of experience in FPGA Verilog design, technology, and tools
- Experience in developing RTL designs in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc.
- Proficient in debugging RTL code using simulation tools
- Excellent ability to analyze and isolate RTL and test bench issues
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experience in HW testing, including working with test equipment, logic and traffic analyzers, test generators, etc.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Scripting language experience: Perl, Python, Makefile, shell preferred.
- Experience in C programming ...