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Design for Testability Engineering Lead

eInfochips (An Arrow Company) | India, India | Posted June 06, 2026

Position Overview

DFT Lead - 7 to 15 Years

Job Location : Bangalore| Hyderabad | Noida | Ahmedabad | Chennai


(NO WORK FROM HOME OR REMOTE WORK)


Job Specs:


- In depth knowledge of DFT concepts


- In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis


- In depth knowledge and hands on experience in MBIST insertion and Memory test validation


- Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations


- Expertise in scripting languages such as perl, shell, etc.


- Experience in RTL and Gate level simulations of scan and MBIST test vectors


- Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)


- Working experience in Synopsis TetraMax/DFTMax and Cadence Encou...

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