ARQUIMEA is a technology company operating globally and providing innovative solutions and products in demanding sectors.
¿Es usted el solicitante adecuado para esta oportunidad? Descúbralo leyendo el resumen del puesto a continuación.
Our areas of activity include Aerospace, Defense & Security, Big Science, Biotechnology and Fintech.
Backend ASIC/FPGA Engineer – Synthesis, Place & Route, and Timing Closure
This position is located at our headquarters in Madrid, Calle Serrano Galvache 56.
Core Functions
Own and execute backend implementation flows for ASIC and/or FPGA designs.
Perform logic synthesis, constraint development, optimization, and design quality checks.
Run place and route flows, including floorplanning, placement, clock tree synthesis, routing, and physical optimization.
Drive static timing analysis and timing closure across multiple modes and corners.
Analyze and resolve timing, congestion, area, power, and signal integrit...