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Analog IC Layout Engineer

Chipright | ireland, Ireland | Posted June 03, 2026

Position Overview

Senior Analog IC Layout Engineer
  • Experienced analog IC layout,
  • Coarse geometry, 0.35um CMOS
  • Experience in Cadence tools , ASSURA DRC LVS , PVS DRC LVS, and QRC
  • Experience in Mentor Calibre Tools DRC LVS and Parasitic Extraction

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